In regards to the current state of quantum computing hardware, with small amounts of available qubits and short decoherence times, it has become an important topic in quantum computing research to simplify quantum circuits by reducing their overall required gate count. An elegant way to reason about quantum circuit simplication is the the graphical rewrite-rule-set of ZX- calculus that allows a exible way of calculating and substituting semantically equivalent parts in quantum algorithms. In 2020, Duncan et al. proposed a way of simplifying quantum circuits via ZX-calculus. However the algorithm's strength is mainly in the reduction of single-qubit gates. While this is well-desired in the eld of quantum error correction, it poses less signicance for practical quantum computation. In practical quantum computation a reduction of 2-qubit-gates is more useful, as that can improve decoherence times and overall qubit-count. For that reason, Staudacher et al. presented an approach to reduce 2-qubit-gate counts in Duncan et al.'s strategy, by introducing heuristics to the existing ZX-rules. These heuristics work with simplication-rules that lead to an overall decrease in 2-qubit-gates. The goal of this thesis is to improve Staudacher et al.'s 2-qubit-gate reduction algorithm. Staudacher et al.'s heuristics-based approach could achieve even more 2-qubit-gate reductions by providing a look-ahead tree for n ∈ N time-steps of possible ZX-rule applications. This is useful in potential scenarios where applying a bad rule (that might even increase the 2-qubit-gate count) allows for better reductions in the next steps that could not be achieved otherwise. This work aims to implement such look-ahead and observe its eects on the algorithm's 2-qubit-gate reduction count.

Tasks:

- Research efficient look-ahead implementations in similar cases (e.g. graph transformations)
- Implement a lookahead functionality into Staudacher et al.'s code
- Evaluate the 2-qubit-gate counts in a table, for n = 0, 1, 2 and 3 look-ahead-steps on benchmark circuits

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**Dauer der Arbeit:**

- gemäß Studienordnung

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1

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